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eLibrary > BS EN 60947-2:2006+A2:2013 Low-voltage switchgear and controlgear - Circuit-breakers >

BS EN 60947-2:2006+A2:2013 Low-voltage switchgear and controlgear - Circuit-breakers, 2013

English [Go to Page]
CONTENTS
1 General [Go to Page]
1.1 Scope and object
1.2 Normative references
2 Definitions
3 Classification
4 Characteristics of circuit-breakers [Go to Page]
4.1 Summary of characteristics
4.2 Type of circuit-breaker
4.3 Rated and limiting values of the main circuit
4.4 Utilization categories
4.5 Control circuits
4.6 Auxiliary circuits
4.7 Releases
4.8 Integral fuses (integrally fused circuit-breakers)
5 Product information [Go to Page]
5.1 Nature of the information
5.2 Marking
5.3 Instructions for installation, operation and maintenance
6 Normal service, mounting and transport conditions
7 Constructional and performance requirements [Go to Page]
7.1 Constructional requirements
7.2 Performance requirements
7.3 Electromagnetic compatibility (EMC)
8 Tests [Go to Page]
8.1 Kind of tests
8.2 Compliance with constructional requirements
8.3 Type tests
8.4 Routine tests
Annexes [Go to Page]
Annex A (normative) Co-ordination under short-circuit conditions between a circuit-breaker and another short-circuit protective device associated in the same circuit
Annex B (normative) Circuit-breakers incorporating residual current protection
Annex C (normative) Individual pole short-circuit test sequence
Annex D Vacant
Annex E (informative) Items subject to agreement between manufacturer and user
Annex F (normative) Additional tests for circuit-breakers with electronic over-current protection
Annex G (normative) Power loss
Annex H (normative) Test sequence for circuit-breakers for IT systems
Annex J (normative) Electromagnetic compatibility (EMC) – Requirements and test methods for circuit-breakers
Annex K (informative) Glossary of symbols related to products covered by this standard
Annex L (normative) Circuit-breakers not fulfilling the requirements for overcurrent protection
Annex M (normative) Modular residual current devices (without integral current breaking device)
Annex N (normative) Electromagnetic compatibility (EMC) – Additional requirements and test methods for devices not covered by Annexes B, F and M
Annex O (normative) Instantaneous trip circuit-breakers (ICB)
Bibliography
Figures [Go to Page]
Figure 1 – Test arrangement (connecting cables not shown) for short-circuit tests
Figure A.1 – Over- current co-ordination between a circuit-breaker and a fuse or back-up protection by a fuse: operating characteristics
Figure A.2 Figure A.3 – Total discrimination between two circuit-breakers
Figure A.4 Figure A.5 – Back-up protection by a circuit-breaker – Operating characteristics
Figure A.6 – Example of test circuit for conditional short-circuit breaking capacity tests showing cable connections for a 3-pole circuit-breaker (C1)
Figure B.1 – Test circuit for the verification of the operating characteristic (see B.8.2)
Figure B.2 – Test circuit for the verification of the limiting value of the non-operating current under over-current conditions (see B.8.5)
Figure B.3 – Test circuit for the verification of the behaviour of CBRs classified under B.3.1.2.2 (see B.8.9)
Figure B.4 – Current ring wave 0,5 µs/100 kHz
Figure B.5 – Example of test circuit for the verification of resistance to unwanted tripping
Figure B.6 – Surge current wave 8/20 µs
Figure B.7 – Test circuit for the verification of resistance to unwanted tripping in case of flashover without follow-on current (B.8.6.2)
Figure B.8 – Test circuit for the verification of the correct operation of CBRs, in the case of residual pulsating direct currents (see B.8.7.2.1, B.8.7.2.2 and B.8.7.2.3)
Figure B.9 – Test circuit for the verification of the correct operation of CBRs, in the case of a residual pulsating direct current superimposed by a smooth direct residual current (see B.8.7.2.4)
Figure F.1 – Representation of test current produced by back-to-back thyristors in accordance with F.4.1
Figure F.2 – Test circuit for immunity and emission tests in accordance with F.4.1.3, F.4.2, F.4.3, F.4.6, F.4.7.1, F.5.4 and F.6.2 – Two phase poles in series
Figure F.3 – Test circuit for immunity and emission tests in accordance with F.4.1.3, F.4.2, F.4.3, F.4.6, F.4.7.1, F.5.4 and F.6.2 – Three phase poles in series
Figure F.4 – Test circuit for immunity and emission tests in accordance with F.4.1.3, F.4.2, F.4.3, F.4.6, F.4.7.1, F.5.4 and F.6.2 – Three-phase connection
Figure F.5 – Test current for the verification of the influence of the current dips and interruptions in accordance with F.4.7.1
Figure F.6 – Circuit for electrical fast transients/bursts (EFT/B) immunity test in accordance with F.4.4 – Two phase poles in series
Figure F.7 – Circuit for electrical fast transients/bursts (EFT/B) immunity test in accordance with F.4.4 – Three phase poles in series
Figure F.8 – Circuit for electrical fast transients/bursts (EFT/B) immunity test in accordance with F.4.4 – Three-phase connection
Figure F.9 – Test circuit for the verification of the influence of surges in the main circuit (line-to-earth) in accordance with F.4.5 – Two phase poles in series
Figure F.10 – Test circuit for the verification of the influence of surges in the main circuit (line-to-earth) in accordance with F.4.5 – Three phase poles in series
Figure F.11 – Test circuit for the verification of the influence of surges in the main circuit (line-to-earth) in accordance with F.4.5 – Three-phase connection
Figure F.12 – Test circuit for the verification of the influence of current surges in the main circuit in accordance with F.4.5 – Two phase poles in series
Figure F.13 – Test circuit for the verification of the influence of current surges in the main circuit in accordance with F.4.5 – Three phase poles in series
Figure F.14 – Test circuit for the verification of the influence of current surges in the main circuit in accordance with F.4.5 – Three-phase connection
Figure F.15 – Temperature variation cycles at a specified rate of change in accordance with F.9.1
Figure F.16 – General test set up for immunity tests
Figure F.17 – Test set up for the verification of immunity to radiated r.f. electromagnetic fields
Figure F.18 – Test set up for the verification of immunity to electrical fast transients/bursts (EFT/B) on power lines
Figure F.19 – Test set up for verification of immunity to electrical fast transients/bursts (EFT/B) on signal lines
Figure F.20 – General test set-up for the verification of immunity to conducted disturbances induced by r.f. fields (common mode)
Figure F.21 – Arrangement of connections for the verification of immunity to conducted disturbances induced by r.f. fields – Two phase poles in series configuration
Figure F.22 – Arrangement of connections for the verification of immunity to conducted disturbances induced by r.f. fields – Three phase poles in series configuration
Figure F.23 – Arrangement of connections for the verification of immunity to conducted disturbances induced by r.f. fields – Three-phase configuration
Figure G.1 – Example of power loss measurement according to G.2.1
Figure G.2 – Example of power loss measurement according to G.2.2 and G.2.3
Figure J.1 – EUT mounted in a metallic enclosure
Figure J.2 – Test set up for the measurement of radiated r.f. emissions
Figure J.3 – Test set up for the verification of immunity to electrostatic discharges
Figure J.4 – Test set up for the verification of immunity to radiated r.f. electromagnetic fields
Figure J.5 – Test set up for the verification of immunity to electrical fast transients/bursts (EFT/B) on power lines
Figure J.6 – Test set up for the verification of immunity to electrical fast transients/bursts (EFT/B) on signal lines
Figure K.1 – Relationship between symbols and tripping characteristics
Figure M.1 – Test circuits for the verification of operation in the case of a steady increase of residual current
Figure M.2 – Test circuits for the verification of operation in the case of a sudden appearance of residual current (with breaking device)
Figure M.3 – Test circuits for the verification of operation in the case of a sudden appearance of residual current (without breaking device)
Figure M.4 – Test circuits for the verification of the limiting value of non-operating current under overcurrent conditions
Figure M.5 – Test circuits for the verification of the resistance to unwanted tripping in the case of loading of the network capacitance
Figure M.6 – Test circuit for the verification of the resistance to unwanted tripping in the case of flashover without follow-on current
Figure M.7 – Test circuits for the verification of operation in the case of a continuous rise of a residual pulsating direct current
Figure M.8 – Test circuits for the verification of operation in the case of a sudden appearance of residual pulsating direct current (without breaking device)
Figure M.9 – Test circuits for the verification of operation in the case of a sudden appearance of residual pulsating direct current (with breaking device)
Figure M.10 – Test circuits for the verification of operation in the case of a residual pulsating direct current superimposed by smooth direct current of 6 mA
Figure M.11 – Test circuits for the verification of operation in the case of a slowly rising residual smooth direct current
Figure M.12 – Test circuits for the verification of operation in the case of a sudden appearance of residual smooth direct current (without breaking device)
Figure M.13 – Test circuits for the verification of operation in the case of a sudden appearance of residual smooth direct current (with breaking device)
Figure M.14 – Test circuits for the verification of operation in the case of a slowly rising residual current resulting from a fault in a circuit fed by a three-pulse star or a six-pulse bridge connection
Figure M.15 – Test circuits for the verification of operation in the case of a slowly rising residual current resulting from a fault in a circuit fed by a two-pulse bridge connection line-to-line
Figure M.16 – Test circuit for the verification of the behaviour of MRCDs with separate sensing means in the case of a failure of the sensor means connection
Figure M.17 – Test circuit for the verification of the behaviour of MRCD with separate sensing means under short-circuit conditions
Figure M.18 – Test circuit for the verification of the behaviour of MRCD with integral sensing means under short-circuit conditions
Figure M.19 – Test circuit for the verification of the behaviour of terminal type MRCD under short-circuit conditions
Figure M.20 – Verification of immunity to radiated r.f. electromagnetic fields – Test set-up for MRCD with separate sensing means (additional to the test of Annex B)
Figure M.21 – Verification of immunity to electrical fast transients/bursts (EFT/B) on the sensing means connection of an MRCD with separate sensing means (additional to the test of Annex B)
Figure M.22 – Verification of immunity to conducted disturbances induced by r.f. fields – Test set up for MRCD with separate sensing means (additional to the test of Annex B)
Tables [Go to Page]
Table 1 – Standard ratios between Ics and Icu
Table 2 – Ratio n between short-circuit making capacity and short-circuit breaking capacity and related power factor (for a.c. circuit-breakers)
Table 3 – Minimum values of rated short-time withstand current
Table 4 – Utilization categories
Table 5 – Preferred values of the rated control supply voltage, if different from that of the main circuit
Table 6 – Characteristics of the opening operation of inverse time-delay over-current opening releases at the reference temperature
Table 7 – Temperature-rise limits for terminals and accessible parts
Table 8 – Number of operating cycles
Table 9 – Overall schema of test sequences
Table 9a – Applicability of test sequences according to the relationship between Ics, Icu and Icw
Table 10 – Number of samples for test
Table 11 – Values of power factors and time constants corresponding to test currents
Table 12 – Test circuit characteristics for overload performance
Table B.1 – Operating characteristic for non-time-delay type
Table B.2 – Operating characteristic for time-delay-type having a limiting non-actuating time of 0,06 s
Table B.3 – Requirements for CBRs functionally dependent on line voltage
Table B.4 – Additional test sequences
Table B.5 – Tripping current range for CBRs in case of an earth fault comprising a d.c. component
Table F.1 – Test parameters for current dips and interruptions
Table J.1 – EMC – Immunity tests
Table J.2 – Reference data for immunity test specifications
Table J.3 – EMC – Emission tests
Table J.4 – Reference data for emission test specifications
Table M.1 – Product information
Table M.2 – Requirements for MRCDs with voltage source
Table M.3 – Test sequences
Untitled [Go to Page]

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BS EN 60947-2:2006+A2:2013 Low-voltage switchgear and controlgear - Circuit-breakers, 2013

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